Integrated circuit (IC) fabrication is a very complex process involving photolithography as one of the most complex techniques, which is an important driving force to promote the development of IC technology and directly determines performance of the resulting chips.
A typical photolithography process involves embodying the design of a circuit layout being manufactured in a mask and then transferring the circuit layout on a silicon substrate after the circuit layout has been enlarged by a photolithography tool. During this process, however, due to the nature of light and limitations of the actually used projection exposure system, serious energy loss may be caused by limited diffraction or non-linear filtering of the imaging system. That is, optical proximity effect (OPE) occurs, which will inevitably produce distortions during the enlargement and transfer of the circuit layout. Such distortions, particularly for processes of 180-micron node or beyond, may have such a great impact as to lead to failure of the whole process. In order to prevent this from happening, optical proximity correction (OPC) methods are used in this art to perform pre-correction on the circuit layout to compensate for the OPE-caused errors.
However, there are still a number of limitations associated with these OPC processes. For example, as shown in FIG. 1, in a mask including six first cells a1, a2, a3, a4, a5, a6 and one second cell b, an overlap between the cells b and a4 renders the cell a4 different from the other cells a1, a2, a3, a5 and a6. Further consideration on the effects of optical interference and diffraction reveals that there is also an overlap between the cell b and an interference-diffraction region a3′ of the cell a3. That is, similar to the cell a4, the cell a3 is also different from the other cells. Therefore, in order for the correctness of an OPC process to be performed, differentiation among the cells a1, a2, a3, a4, a5, a6 is needed.